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19-1729; Rev 1; 7/03
KIT ATION EVALU ILABLE AVA
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
General Description Features
o Single 3.0V Operation o Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power: 30mA (Normal Operation) 5A (Shutdown Mode) o Fully Differential Analog Input o Wide 2Vp-p Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package
MAX1446
The MAX1446 10-bit, 3V analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1446 operates from a single 2.7V to 3.6V supply, consuming only 90mW while delivering a 59.5dB signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1446 features a 5A power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower and higher speed, pin-compatible versions of the MAX1446 are also available. Refer to the MAX1444 data sheet for a 40Msps version and the MAX1448 data sheet for a 80Msps version. The MAX1446 has parallel, offset binary, three-state outputs that can be operated from 1.7V to 3.3V to allow flexible interfacing. The device is available in a 5x5mm, 32-pin TQFP package and is specified over the extended industrial (-40C to +85C) temperature range.
Ordering Information
PART MAX1446EHJ TEMP RANGE -40C to +85C PIN-PACKAGE 32 TQFP
Functional Diagram
________________________Applications
Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications
CLK MAX1446 CONTROL
VDD GND
IN+ T/H INPIPELINE ADC
D E C
10
OUTPUT DRIVERS
D9-D0
PD
REF
REF SYSTEM + BIAS
OVDD OGND
REFOUT REFIN REFP COM REFN
OE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9-D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 32-Pin TQFP (derate 11.1mW/C above +70C)...........889mW Operating Temperature Range ..........................-40C to +85C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, OVDD = 2.7V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 62.5MHz, 4096-point FFT) fIN = 7.492MHz Signal-to-Noise Ratio SNR fIN = 19.943MHz fIN = 39.9MHz (Note 1) Signal-to-Noise Plus Distortion (up to 5th Harmonic) fIN = 7.492MHz SINAD fIN = 19.943MHz fIN = 39.9MHz (Note 1) Spurious-Free Dynamic Range fIN = 7.492MHz SFDR fIN = 19.943MHz fIN = 39.9MHz (Note 1) 65 63 56.6 56.2 57 56.5 59.5 59.5 59 59.4 59 58.5 74 73 71 dBc dB dB fCLK 60 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs 1.0 VDD/2 0.5 33 5 V V k pF INL DNL fIN = 7.492MHz, TA +25C No missing codes, fIN = 7.492MHz -1.6 10 0.6 0.4 <0.1 0 1.9 1.0 1.9 2.0 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 2.7V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.Typical values are at TA = +25C.)
PARAMETER Third-Harmonic Distortion Two-Tone Intermodulation Distortion Third-Order Intermodulation Distortion Total Harmonic Distortion (First 5 Harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation EXTERNAL REFERENCE Positive Reference Negative Reference Differential Reference Voltage REFIN Resistance DIGITAL INPUTS (CLK, PD, OE ) CLK Input High Threshold VIH PD, OE 0.8 x VDD 0.8 x OVDD REFP REFN VREF RREFIN VREFIN = 2.048V VREFIN = 2.048V VREFP - VREFN, VREFIN = 2.048V, TA +25C 0.98 2.012 0.988 1.024 >50 1.07 V V V M REFOUT TCREF 2.048 1% 60 1.25 V ppm/C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 x full-scale input SYMBOL HD3 CONDITIONS fIN = 7.492MHz fIN = 19.943MHz fIN = 39.9MHz (Note 1) IMDTT IM3 f1 = 19MHz at -6.5dBFS, f2 = 21MHz at -6.5dBFS (Note 2) f1 = 19MHz at -6.5dBFS f2 = 21MHz at -6.5dBFS (Note 2) fIN = 7.492MHz THD fIN = 19.943MHz fIN = 39.9MHz (Note 1) Input at -20dBFS, differential inputs Input at -0.5dBFS, differential inputs MIN TYP -74 -73 -71 -75 -75 -70 -70 -69 500 400 1 2 2 1 0.25 0.2 MHz MHz ns psrms ns % LSBrms -64 -63 dBc dBc dBc dBc MAX UNITS
MAX1446
V
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3
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 2.7V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential with respect to COM), CL 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.Typical values are at TA = +25C.)
PARAMETER SYMBOL CLK Input Low Threshold VIL PD, OE Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (D9-D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current VDD OVDD IVDD CL = 10pF Operating, fIN = 19.943MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fIN = 19.943MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid OE Fall to Output Enable OE Rise to Output Disable CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 5 (Note 3) Figure 5 Figure 5 Figure 6, clock period 16ns Figure 6, clock period 16ns (Note 4) 5 10 1.5 8.3 2.5 8.3 2.5 1.5 8 ns ns ns ns ns s PSRR Offset Gain 2.7 1.7 3.0 3.0 30 4 7 1 0.1 0.1 20 3.6 3.6 37 15 V V mA A mA A mV/V %/V VOL VOH ILEAK COUT ISINK = 200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD 0.2 10 0.2 V V A pF VHYST IIH IIL CIN VIH = VDD = OVDD VIL = 0 5 0.1 5 5 CONDITIONS MIN TYP MAX 0.2 x VDD 0.2 x OVDD V A pF UNITS
V
Output Supply Current
IOVDD
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. 4 _______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
Typical Operating Characteristics
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L 10pF, T A = +25C, unless otherwise noted.)
FFT PLOT fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 2ND HARMONIC 3RD HARMONIC SFDR = 72.2dB SNR = 60.1dB THD = -71.5dB SINAD = 59.8dB AMPLITUDE (dB)
MAX1446
FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1446 toc01
FFT PLOT (fIN = 20MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 3RD HARMONIC 2ND HARMONIC SINAD = 59.3dB SNR = 59.6dB THD = -70.7dBc SFDR = 72.2dBc
MAX1446 toc03 MAX1446 toc11 MAX1446 toc06
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 2ND HARMONIC
SFDR = 72.2dBc SNR = 60.1dB THD = -71.5dBc SINAD = 59.8dB
0
3RD HARMONIC
25
30
35
0
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (fIN = 26.8MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 2ND HARMONIC 3RD HARMONIC
FFT PLOT (fIN = 50MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1446 toc04
FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
MAX1446 toc05
SINAD = 59.0dB SNR = 59.4dB THD = -70.5dBc SFDR = 72.9dBc
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100
SFDR = 70dBc SNR = 59.1dB THD = -67.1dBc SINAD = 58.5dB
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 2ND HARMONIC
SINAD = 59.5dB SNR = 59.7dB THD = -73.0dBc SFDR = 73.6dBc
3RD HARMONIC 2ND HARMONIC
3RD HARMONIC
35
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (fIN = 20MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
MAX1446 toc07
TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 50 0 5 10 15 20 25 30 35 1 SINAD (dBc) f1 = 19MHz AT -6.5dBFS f2 = 21MHz AT -6.5dBFS 3RD IMD = -76dBc
MAX1446 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
80 DIFFERENTIAL 75 70 65 60 55 SINGLE ENDED
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 3RD HARMONIC
SINAD = 59.2dB SNR = 59.5dB THD = -70.7dBc SFDR = 71.1dBc
0
2ND HARMONIC
25
30
35
10 ANALOG INPUT FREQUENCY (MHz)
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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5
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L 10pF, T A = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1446 toc12
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1446 toc13
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
DIFFERENTIAL 59 58
MAX1446 toc14
60 SINGLE ENDED 59 DIFFERENTIAL
-50
60
-55
THD (dBc)
SNR (dB)
-60
SINGLE ENDED
SINAD (dB)
57 SINGLE ENDED 56 55 54
58
-65
57 -70
53 56 1 10 ANALOG INPUT FREQUENCY (MHz) 100 DIFFERENTIAL -75 1 10 ANALOG INPUT FREQUENCY (MHz) 100 52 1 10 ANALOG INPUT FREQUENCY (MHz) 100
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
MAX1446 toc15
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1446 toc16
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
fIN = 19.943MHz -55 -60 THD (dBc) -65 -70 -75 -80
MAX1446 toc17
80 fIN = 19.943MHz 75 70 SFDR (dBc) 65 60 55 50 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
66 fIN = 19.943MHz 60 54 SNR (dB) 48 42 36 30 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS)
-50
-20
-16
-12
-8
-4
0
ANALOG INPUT POWER (dBFS)
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER
MAX1446 toc18
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1446 toc19
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
fIN = 19.943MHz 66
MAX1446 toc20
65 fIN = 19.943MHz 60 55 SINAD (dB)
80 fIN = 19.943MHz 76
70
SFDR (dBc)
50 45 40
SNR (dB)
72
62
68
58
64 35 30 -20 -16 -12 -8 -4 0 ANALOG INPUT POWER (dBFS) 60 -40 -15 10 35 60 85 TEMPERATURE (C)
54
50 -40 -15 10 35 60 85 TEMPERATURE (C)
6
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L 10pF, T A = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
MAX1446 toc21
MAX1446
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
MAX1446 toc22
70 fIN = 19.943MHz 66
-60 fIN = 19.943MHz -64
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)
0.4 0.3 fIN = 7.5MHz
MAX1446 toc23
0.5
SINAD (dB)
62
INL (LSB)
-68
0.2 0.1 0
58
-72
54
-76
-0.1 -0.2
50 -40 -15 10 35 60 85 TEMPERATURE (C)
-80 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.3 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE GAIN ERROR (LSB) fIN = 7.5MHz
MAX1446 toc24
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V)
MAX1446 toc25
OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V)
8 6 OFFSET ERROR (LSB) 4 2 0 -2 -4 -6 -8 -10
MAX1446 toc26
0.3
10 8 6 4 2 0 -2 -4 -6 -8 -10 -40 -15 10 35 60
10
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1446 toc27
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1446 toc28
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
fIN = 7.5MHz 7 6
MAX1446 toc29
35
32
8
33
31
IVDD (mA)
31
IOVDD (mA) -40 -15 10 35 60 85
IVDD (mA)
30
5 4
29
29
27
28
3 2 1.2 1.8 2.4 OVDD (V) 3.0 3.6 TEMPERATURE (C)
25 2.70
27 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
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7
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L 10pF, T A = +25C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX1446 toc30
ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY
OE = OVDD, PD = VDD
MAX1446 toc31
DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY
PD = VDD, OE = OVDD 8
MAX1446 toc32
8 fIN = 7.5MHz 7
5.0 4.5 4.0 3.5 3.0
10
IOVDD (mA)
5
IOVDD (A)
IVDD (A)
6
6
4
4 2.5 3 -40 -15 10 35 60 85 TEMPERATURE (C) 2.0 2.70
2
0 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 1.2 1.8 2.4 OVDD (V) 3.0 3.6
SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY
MAX1446 toc33
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1446 toc34
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1446 toc35
80
SFDR
fIN = 20MHz
2.10
2.10
SFDR, SNR, THD, SINAD (dB)
74
2.08 VREFOUT (V)
2.08 VREFOUT (V)
68
THD SNR
2.06
2.06
62
2.04
2.04
56
SINAD
2.02
2.02
50 50 54 58 62 66 70 CLOCK FREQUENCY (MHz)
2.00 2.70
2.85
3.00
3.15 3.30 VDD (V)
3.45
3.60
2.00 -40
-15
10 35 TEMPERATURE (C)
60
85
OUTPUT NOISE HISTOGRAM (DC INPUT)
140000 120000 COUNTS 100000 80000 60000 40000 20000 0 0 N-2 N-1 N N+1 N+2 DIGITAL OUTPUT CODE 926 725 0
MAX1446 toc36
160000 129421
8
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
Pin Description
PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 NAME REFN COM VDD GND IN+ INCLK PD FUNCTION Lower Reference. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. Common-Mode Voltage Output. Bypass to GND with a >0.1F capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Analog Ground Positive Analog Input. For single-ended operation, connect signal source to IN+. Negative Analog Input. For single-ended operation, connect IN- to COM. Conversion Clock Input Power-Down Input High: power-down mode Low: normal operation Output Enable Input High: digital outputs disabled Low: digital outputs enabled Three-State Digital Outputs D9-D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4-D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >0.01F capacitor. Upper Reference. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor.
MAX1446
15 16-20 21 22 23 24-28 29 31 32
OE D9-D5 OVDD T.P. OGND D4-D0 REFOUT REFIN REFP
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9
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
Detailed Description
The MAX1446 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. input. The resulting differential voltage is held on C2a and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output, and S4c is closed. This charges C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1446 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs (IN+ and IN-) can be driven either differentially or single ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1446 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC's full-scale range is user adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs.
INTERNAL BIAS S2a C1a COM S5a S3a
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the input T/H circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b). S2a and S2b set the common mode for the amplifier
MDAC VIN T/H x2 VOUT
S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM
FLASH ADC 1.5 bits
DAC
IN-
VIN
STAGE 1
STAGE 2
STAGE 10
DIGITAL CORRECTION LOGIC 10 D9-D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED) TRACK HOLD TRACK CLK
INTERNAL HOLD NON-OVERLAPPING CLOCK SIGNALS
Figure 1. Pipelined Architecture--Stage Blocks 10
Figure 2. Internal T/H Circuit
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
The MAX1446 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10k) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. The MAX1446 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle.
MAX1446
Output Enable (OE), Power-Down (PD), and Output Data (D0-D9)
All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. The capacitive load on the digital outputs D0-D9 should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1446, degrading its dynamic performance. The use of buffers on the ADC's digital outputs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1446 small series resistors (e.g. 100) may be added to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid.
Clock Input (CLK)
The MAX1446 CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC as follows: SNR = 20log (1 / 2fINtAJ) where fIN represents the analog input frequency, and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
System Timing Requirements
Figure 6 shows the relationship between the clock input, analog input, and data output. The MAX1446 samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles.
Table 1. MAX1446 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 511/512 VREF x 510/512 VREF x 1/512 0 - V REF x 1/512 - V REF x 511/512 - V REF x 512/512 DIFFERENTIAL INPUT +Full Scale -1LSB +Full Scale -2LSB +1LSB Bipolar Zero -1LSB Negative Full Scale + 1LSB Negative Full Scale STRAIGHT OFFSET BINARY 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000
*VREFIN = VREFP = VREFN ______________________________________________________________________________________ 11
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
80 fIN = 12.5MHz AT -0.5dBFS 70 SFDR (dBc) THD (dBc) -50 -40 fIN = 12.5MHz AT -0.5dBFS
60
-60
50
-70
40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%)
-80 20 30 40 50 60 70 CLOCK DUTY CYCLE (%)
Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)
Figure 4a. THD vs. Clock Duty Cycle (Differential Input)
70 fIN = 12.5MHz AT -0.5dBFS 65 60 SINAD (dB) SNR (dB) 55 50 45 40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%)
70 fIN = 12.5MHz AT -0.5dBFS 65 60 55 50 45 40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%)
Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)
Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)
Figure 6 also shows the relationship between the input clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
12
RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 7, an RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution for converting a single-ended source signal to a fully differential signal, required by the MAX1446 for optimum performance. Connecting the transformer's center tap to COM provides a VDD/2 DC level shift to
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1446 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower since both inputs (IN+, IN-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
MAX1446
Grounding, Bypassing, __________________and Board Layout
The MAX1446 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider using a split ground plane arranged to match the physi-
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
OE
tENABLE OUTPUT DATA D9-D0 HIGH-Z
tDISABLE HIGH-Z
VALID DATA
Figure 5. Output Enable Timing
5.5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
CLOCK INPUT tDO N-6 N-5 N-4 tCH N-3 tCL N-2 N-1 N N+1
DATA OUTPUT
Figure 6. System and Output Timing Diagram ______________________________________________________________________________________ 13
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F RISO 50 0.1F CIN 22pF IN-
-5V
MAX1446
600 300 600 COM 0.1F +5V +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 IN+ RISO 50 0.1F CIN 22pF LOWPASS FILTER 600
-5V
300 -5V
300 300 600
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
cal location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital
14
signal traces away from sensitive analog traces. Keep all signal lines short and free of 90 turns.
Static Parameter Definitions
Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The MAX1446's static linearity parameters are measured using the best-straight-line fit method.
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10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference
25 IN+ 22pF 0.1F VIN 1 N.C. 2 3 T1 6 5 4 2.2F 0.1F MAX1446
Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR(MAX) = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the rms signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is computed from: ENOB = (SINAD - 1.76dB) / 6.02dB
MAX1446
COM
MINICIRCUITS TT1-6 25 IN22pF
Figure 8. Using a Transformer for AC-Coupling
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
REFP
VIN MAX4108 100
1k 0.1F RISP IN+ CIN 1k
MAX1446
COM 0.1F RISO
REFN
100 RISO = 50 CIN = 22pF
INCIN
Figure 9. Single-Ended AC-Coupled Input
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15
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446
CLK
Pin Configurations (continued)
REFOUT
TOP VIEW
REFIN REFP GND
D0
D1
D2 26
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) REFN COM VDD GND T/H TRACK HOLD TRACK GND IN+ IN1 2 3 4 5 6 7 8
32
31
30
29
28
27
D3 25 24 D4 23 OGND 22 T.P. 21 OVDD 20 D5 19 D6 18 D7 17 D8 16 D9
MAX1446
Figure 10. T/H Aperture Timing
GND
Total Harmonic Distortion (THD) THD is typically the ratio of the rms sum of the input signal's first four harmonics to the fundamental itself. This is expressed as: THD = 20 x log
9 VDD
10 VDD
11 GND
12 CLK
13 PD
14 GND
15 OE
(
V22 + V32 + V42 + V52 / V1
)
TQFP
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale, and their envelope is at -0.5dB full scale.
Chip Information
TRANSISTOR COUNT: 5684 PROCESS: CMOS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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